Low-speed transmission of multi-bit words typically occurs over multi-wire buses with the bits for each multi-bit word being transmitted in parallel. For example, an eight-bit word may be transmitted over a bus having eight wires, one for each bit. But in such conventional buses, each bit carried on a given wire is independent of the remaining bits. As the data rates increase, the parallel data communication becomes problematic in that the various bits in a word become skewed from each other as the word propagates over the bus.
Given the issues with skew between multiple bits in high-speed communication, various serializer/deserializer (SerDes) systems have been developed. A SerDes transmitter serializes a multi-bit word into a series of corresponding bits for transmission to a receiver. There can then be now skew due to the serial transmission (although there may be multiple SerDes transmitters arranged in parallel with each SerDes transmitter transmitting over its serial data stream). The SerDes receiver deserializes the received serial bit stream into the original word.
SerDes systems may be either source synchronous or use an embedded clock. In a source synchronous system, the SerDes transmitter is associated with a SerDes clock transmitter for transmitting a clock signal with the serialized data stream. A SerDes receiver in a source synchronous system thus does not need to recover an embedded clock signal from the data using a clock data recovery (CDR) circuit. However, a source synchronous SerDes receiver still includes a CDR circuit that uses a local clock signal to align the received clock signal with the data eye for the received serial data stream. The receiver, transmitter, and clock transmitter in a source synchronous SerDes system thus all require a local clock signal for their operation.
An example source synchronous SerDes system 100 is shown in FIG. 1. A phase-locked loop (PLL) 105 generates a half-rate clock signal and its inverse in both in-phase (I) and quadrature (Q) forms such that the half-rate clock signal has four phases such as 0 degrees, 90 degrees, 180 degrees and 270 degrees. A transmitter (TX) 110 serializes a data stream for transmission responsive to two of the half-rate clock phases. In particular, transmitter 110 samples a parallel data stream being serialized responsive to a first clock edge (rising or falling) of the half-rate clock signal Transmitter 110 also samples the parallel data stream responsive to the same type of edge (the second edge being a rising edge if the first edge was rising and being a falling edge if the first edge was falling) of the inverse of the half-rate clock signal. It will be appreciated that transmitter 110 could perform this serialization using just one half-rate clock signal if it sampled responsive to both clock edges. Similarly, a clock transmitter (TX (CLK)) 120 generates the data clock signal responsive to the half-rate clock signal and its inverse. In contrast, a receiver (RX) 115 uses all four phases of the half-rate clock signal in its CDR circuit (not illustrated) as noted above so that the resulting aligned clock signal from the CDR circuit may be used to sample the received serial data stream to produce a parallel (de-serialized) data stream.
The data rate for the serialized data stream transmitted by transmitter 110 and de-serialized by receiver 115 is twice the half-rate clock frequency for PLL 105. Thus, if the data rate is 10 GHz, the half-rate clock frequency is 5 GHz. But as the data rate is increased, operation of system 100 becomes problematic. In particular, note that PLL 105 and transmitters 110 and 115 as well as receiver 120 may be widely separated on an integrated circuit die such as for a system-on-a-chip (SoC). The four phases of the half-rate clock signal must thus travel on respective leads (e.g., a trace in a metal layer) from PLL 105 to receiver 115. Similarly, two of the phases of the half-rate clock signal must travel on respective leads from PLL 105 to transmitters 110 and 120. These transmission lines may extend for as much as a millimeter or more across the SoC die. Should the data rate increase to 20 GHz, the various phases of the 10 GHz half-rate clock signal will tend to skew unacceptably with respect to each other as they propagate down such relatively long transmission lines. In addition, parasitic capacitance for such relatively long transmission lines may cause unacceptably high loss of the clock signal. Moreover, even if skew can be maintained within acceptable limits, PLL 105 will tend to consume substantial power at such elevated clocking rates. These issues of skew and power consumption are also present for embedded clock SerDes systems since their transmitters also need a half-rate clock signal.
Accordingly, there is a need in the art for high-data-rate SerDes architectures with reduced skew and power consumption.